| PART |
Description |
Maker |
| KS74AHCT112 |
Dual J-K Negative-Edge-Triggered Flip-Flops
|
Samsung
|
| SN74LS113D SN74LS113N SN54LS113J SN54LS113A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
|
| SN74LS107D SN74LS107N SN54LS107J SN54LS107A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
Motorola Inc
MOTOROLA[Motorola Inc]
|
| PO74G112ATR PO74G112ATU PO74G112ASU PO74G112ASR |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
|
Potato Semiconductor Corporation
|
| MAX768 MAX768EEE MAX768C_D MAX768C/D |
Low-Noise, Dual-Output, Regulated Charge Pump for GaAsFET, LCD, and VCO Supplies
Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125
|
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
| 74HC73 74HC73PW 74HC73D |
Dual JK flip-flop with reset; negative-edge trigger
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors
|
| ACTS112HMSR-02 |
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16
|
HARRIS SEMICONDUCTOR
|
| 74F114SC 74F114 74F114PC |
双JK负沿触发器与普通时钟和清除拖鞋
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
From old datasheet system
|
锁存
FAIRCHILD[Fairchild Semiconductor]
|
